1. Field of the Invention
The present invention relates to a signal processing circuit used in a digital serial interface.
2. Description of the Related Art
In recent years, the IEEE (Institute of Electrical and Electronic Engineers) 1394 high performance serial bus for realizing high speed data transfer and real time transfer has become the standard for interfaces for transfer of multimedia data.
The data transfer of this IEEE 1394 serial interface includes the asynchronous transfer for requests, requests for acknowledgment, and acknowledgment of reception of the related art and isochronous transfer with which the data is sent at one time from a certain node at 125 xcexcs.
Data is transferred in units of packets using an IEEE 1394 serial interface having such two transfer modes.
FIGS. 8A and 8B are views of the byte size of a source packet in isochronous communication. FIG. 8A shows the size of a packet in digital video broadcast (DVB) specifications, while FIG. 8B shows the size of a packet in digital satellite system (DSS) specification.
A source packet in the DVB specification is comprised of 192 bytes, that is, 4 bytes of a source packet header (SPH) and 188 bytes of inherent transport stream data (TSD), as shown in FIG. 8A.
Contrary to this, the source packet in the DSS specification is comprised of 144 bytes, that is, 4 bytes of a source packet header (SPH), 10 bytes of additional data (AD0 to AD9), and 130 bytes of inherent transport stream data (TSD).
The additional bytes are inserted between the source packet header and the data. Note that, in the IEEE 1394 standard, the unit of minimum data able to be handled is one quadlet (=4 bytes=32 bits), therefore the total of the transport stream data and the additional data must be comprised of 32-bit units.
At the default, however, no additional byte is set.
FIG. 9 is a view of an example of the correspondence between the original data and the packets actually transmitted when data is transmitted in the isochronous communication of the IEEE 1394 standard.
As shown in FIG. 9, each of the source packets of the original data is given a source packet header of 4 bytes and padding data for adjusting the data length and then is divided into a predetermined number of data blocks.
Note that since the unit of data when transferring a packet is one quadlet (4 bytes), the byte lengths of the data blocks, various headers, etc. are all set to multiples of 4.
FIG. 10 is a view of the format of the source packet header.
As shown in FIG. 10, a time stamp utilized for suppressing Jitter when for example MPEG (Moving Picture Experts Group)-TS (Transport Stream) data utilized in a digital satellite broadcast etc. of the above DVB specificatoin is transmitted by isochronous communication is written in 25 bits in the source packet header.
Such a packet header, a common isochronous packet (CIP) header, and other data is added to a predetermined number of data blocks so as to produce a final packet.
FIG. 11 is a view of an example of the basic configuration of an isochronous communication use packet.
As shown in FIG. 11, in a packet for isochronous communication, the first quadlet is comprised of a 1394 header, the second quadlet a Header-CRC, the third quadlet a CIP-header 1, the fourth quadlet a CIP-header 2, the fifth quadlet a source packet header (SPH), and the sixth quadlet and on a Data-CRC.
The 1394 header is comprised by a xe2x80x9cdata-lengthxe2x80x9d representing the data length, a xe2x80x9cchannelxe2x80x9d indicating the number of the channel (one of 0 to 63) over which this packet is to be transferred, a xe2x80x9ctcodexe2x80x9d representing a processing code, and a synchronous code xe2x80x9csyxe2x80x9d prescribed by each application.
The Header-CRC is an error detection code of the packet header.
The CIP-header 1 is comprised by a source node ID (SID) region for the number of the transmission node, a data block size (DBS) region for the length of the data block, a fraction number (FN) region for the number of divisions of the data in the formation of the packet, a quadlet padding count (QPC) region for the number of the quadlets of the padding data, a source packet header (SPH) region for the flag showing the existence of the source packet header, and a data block continuity counter (DBC) region for the counter for detecting the number of isochronous packets.
Note that the DBS region shows the number of the quadlets transferred through one isochronous packet.
The CIP-header 2 is comprised by an FMT region for the signal format showing the type of the data to be transferred and a format dependent field (FDF) region utilized corresponding to the signal format.
The SPH header has a time stamp region in which is set a value for giving a fixed delay in the order of arrival of the transport stream packet.
Further, the data CRC is the error detection code of the data field.
A signal processing circuit of an IEEE 1394 serial interface for the transmission and reception of packets having the above configuration is mainly constituted by a physical layer circuit for directly driving the IEEE 1394 serial bus and a link layer circuit for controlling the data transfer of the physical layer circuit.
In the isochronous communication system in the IEEE 1394 serial interface, as shown in for example FIG. 12, the link layer circuit 2 is connected to an application, that is, MPEG transporter 1, while the link layer circuit 2 is connected to a serial interface bus BS via a physical layer circuit 3.
In the transfer of data of the IEEE 1394 serial interface, the transmission data and reception data are stored once in a storage device such as a first-in first-out (FIFO) memory (hereinafter simply referred to as an FIFO) provided in the link layer circuit 2. In actuality, an asynchronous packet use FIFO and an isochronous packet use FIFO are separately provided.
As explained above, one source packet of transport stream data of an ordinary MPEG is sometimes divided for transmission.
However, in the present signal processing circuit of IEEE 1394 serial interface circuit, there is no processing system for dividing one source packet or combining several source packets for transmission.
For example in the present system, as shown in FIG. 13, a data is transmitted when there is data to be transferred. When there is no data to be transmitted, the transmission side is in an idle state with respect to the serial bus.
However, even when the transmission side is in an idle state, the transmission systems of other nodes cannot use the bus since it is necessary to secure the bandwidth for maximum peak time.
An object of the present invention is to provide a signal processing circuit which can efficiently use a serial interface bus.
According to a first aspect of the present invention, there is provided a signal processing circuit for performing transmission between its own node and another node connected to its own node via a serial interface bus, comprising a data processing circuit for dividing an input stream packet based on a predetermined number of divided blocks set in accordance with an input rate for output.
According to a second aspect of the present invention, there is provided a signal processing circuit for performing transmission between its own node and another node connected to its own node via a serial interface bus, comprising a data processing circuit for combining input stream packets based on a predetermined number of synthesized packets set in accordancw with an input rate for output.
According to a third aspect of the present invention, there is provided a signal processing circuit for performing transmission between its own node and another node connected to its own node via a serial interface bus, comprising a data processing circuit for dividing or synthesizing an input stream packet based on a predetermined number of divided blocks or number of synthesized packets set in accordance with an input rate for output.
According to the present invention, for example in the case of transmitting a transport stream packet in the data processing circuit, the transport stream packet to be input is divided or packets are combined based on a number of divided blocks or number of synthesized packets set in advance in response to an input rate and transferred to the serial interface bus.
This number of divided blocks or number of synthesized packets is set in accordance with the peak rate of the stream.
Also, each packet to be transferred to the serial interface bus is given a time stamp for suppressing jitter at the serial interface and determining the data output time at the reception side.